//生成ALU控制信号
module ALUcontrol(clk, reset, ALUop, funct7, funct3, out);
    input wire clk;
    input wire reset;
    input wire[1:0] ALUop;
    input wire[31:25] funct7;
    input wire[14:12] funct3;
    output reg[3:0] out; 

    parameter addOP = 4'b0010;
    parameter subOP = 4'b0110;
    parameter andOP = 4'b0000;
    parameter orOP  = 4'b0001;
    parameter errorOP = 4'b1111;

    always @(posedge reset)
    begin
        out = errorOP;
    end

    always @(ALUop, funct7, funct3)
    begin
        case (ALUop)
            2'b00 : out = addOP;
            2'b01 : out = subOP;
            2'b10 : 
            begin
                case (funct7)
                    7'b0100000 : 
                    begin
                        if(funct3 == 3'b000) out = subOP;
                        else out = errorOP;
                    end 

                    7'b0000000 : 
                    begin
                        case (funct3)
                            3'b000 : out = addOP;
                            3'b111 : out = andOP;
                            3'b110 : out = orOP; 
                            default: out = errorOP;
                        endcase
                    end   
                    default: out = errorOP;
                endcase
            end
            default : out = errorOP; //error 
        endcase
    end

endmodule